<?xml version="1.0" encoding="utf-8" standalone="yes"?>
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/">
  <channel>
    <title>Hardware Design on Sekura</title>
    <link>https://sekura.world/tags/hardware-design/</link>
    <description>Recent content in Hardware Design on Sekura</description>
    <generator>Hugo -- 0.147.7</generator>
    <language>en-us</language>
    <lastBuildDate>Wed, 23 Sep 2026 12:00:00 +0500</lastBuildDate>
    <atom:link href="https://sekura.world/tags/hardware-design/index.xml" rel="self" type="application/rss+xml" />
    <item>
      <title>Formal Verification of SystemVerilog in Memora8: RTL Contracts and Proof Scope</title>
      <link>https://sekura.world/posts/memora8-formal-verification-systemverilog/</link>
      <pubDate>Wed, 23 Sep 2026 12:00:00 +0500</pubDate>
      <guid>https://sekura.world/posts/memora8-formal-verification-systemverilog/</guid>
      <description>How Memora8 applies formal verification to SystemVerilog RTL using machine-checkable contracts, symbolic memory models, and SJP proof records, while clearly separating VERIFIED, FAILED, and UNSUPPORTED results.</description>
    </item>
  </channel>
</rss>
