Memora8: One Week of Simulator Alignment and Formal CPU Verification
During October 19–25, Memora8 advanced its independent C++ emulator and the formal verification of its SystemVerilog RTL. mr8sim gained a more faithful eight-stage pipeline, per-page SRAM port arbitration, word-streamed PageMover and a persistent sparse 8 GiB SD image. Static and dynamic Sekura JS programs passed language tests; selected RTL/C++ traces matched 22/22 and 16/16 COMMIT events. The open Assurance Memora8 repository records 859 proved obligations, 51 expected counterexamples and 51 SJP packages for scoped properties across all 32 opcodes.