Memora8 Documentation

Memora8 Instruction Set Architecture Document version: 0.1 Status: Published specification Implementation baseline: Memora8 commit 61039f1 Overview Memora8 is a 32-bit processor architecture with 32 general-purpose registers and fixed-width, 32-bit instruction words. Its 5-bit opcode field defines 32 opcode values. The instruction set includes integer arithmetic and logic, shifts, comparisons, branches and jumps, 32-bit loads and stores, multiplication, division and remainder, bit search, and privileged System Bus access. MTR is not a program instruction or opcode; trap handling is a processor mechanism. ...