Memora8 Instruction Set Architecture

Document version: 0.1 Status: Published specification Implementation baseline: Memora8 commit 61039f1

Overview

Memora8 is a 32-bit processor architecture with 32 general-purpose registers and fixed-width, 32-bit instruction words. Its 5-bit opcode field defines 32 opcode values.

The instruction set includes integer arithmetic and logic, shifts, comparisons, branches and jumps, 32-bit loads and stores, multiplication, division and remainder, bit search, and privileged System Bus access. MTR is not a program instruction or opcode; trap handling is a processor mechanism.

Registers

The architecture provides 32 general-purpose 32-bit registers, r0 through r31. r0 always reads as zero; writes to it have no effect. Register roles beyond this rule are defined by the ABI.

Encoding

Instructions are little-endian 32-bit words in memory. The opcode is in bits [4:0]. The decoder exposes register fields rd = bits[9:5], rs1 = bits[14:10], and rs2 = bits[19:15]. Immediate instructions use a sign-extended 17-bit value from bits [31:15]; branch and direct-jump instructions use a sign-extended 22-bit offset from bits [31:10].

Fields are interpreted according to the instruction. In particular, SW uses the rd field to select its source value, and conditional branches use that field to select the tested register. This article does not define assembler syntax or require unused bits to have a particular value.

Opcode map

Opcode Instruction Operation
0x00 ADD Add two register values
0x01 ADDI Add a sign-extended immediate
0x02 SUB Subtract register values
0x03 AND Bitwise AND of register values
0x04 ANDI Bitwise AND with an immediate
0x05 OR Bitwise OR of register values
0x06 ORI Bitwise OR with an immediate
0x07 XOR Bitwise XOR of register values
0x08 XORI Bitwise XOR with an immediate
0x09 SHFT Shift using a register control
0x0A SHFTI Shift using an immediate control
0x0B CMP Compare two register values
0x0C CMPI Compare a register with an immediate
0x0D LUI Load an immediate into the upper 16 bits
0x0E AUIPC Add an upper immediate to the current PC
0x0F BNZ Branch if the selected register is nonzero
0x10 BEQZ Branch if the selected register is zero
0x11 JAL PC-relative jump and link
0x12 JALR Register-relative jump and link
0x13 LW Load a 32-bit word
0x14 SW Store a 32-bit word
0x15 MUL Low 32 bits of a product
0x16 MULH High 32 bits of a signed product
0x17 MULHU High 32 bits of an unsigned product
0x18 DIV Signed division
0x19 DIVU Unsigned division
0x1A REM Signed remainder
0x1B REMU Unsigned remainder
0x1C MSB Register-controlled bit search
0x1D MSBI Immediate-controlled bit search
0x1E SB Register-controlled System Bus access
0x1F SBI Immediate-controlled System Bus access

Arithmetic, logic, and shifts

Arithmetic and logical results are 32-bit values. Immediate forms use the sign-extended 17-bit immediate. MUL returns the low 32 product bits; MULH and MULHU return the high 32 bits for signed and unsigned multiplication, respectively.

SHFT and SHFTI use a signed shift control: a negative control shifts left, while a nonnegative control performs a logical right shift. The shift count is the low five bits of the control, so the shift amount is in the range 0 through 31.

Comparisons

CMP and CMPI write a comparison mask to the destination register; they do not set a global condition-code register. The mask bits indicate equality, signed less-than, signed greater-than, unsigned less-than, and unsigned greater-than, respectively, in bits 0 through 4. Software can test these bits with ordinary logical and branch instructions.

Immediate construction and control flow

LUI places the 17-bit immediate in bits [31:16] of the result. AUIPC adds that value to the instruction’s current PC.

BNZ and BEQZ test the register selected by the rd field. Their signed 22-bit offsets are scaled by four bytes and added to the current PC when the branch is taken. JAL uses the same PC-relative offset and writes PC + 4 to its destination. JALR adds its sign-extended 17-bit immediate to rs1 for the target and writes PC + 4 to its destination.

Memory access

LW and SW transfer one 32-bit word. The effective address is rs1 + sign_extended_imm17. LW writes the loaded word to rd; SW stores the value selected by the rd field. The simulator also forwards a pending store to a load of the same word.

System Bus operations are separate from ordinary memory operations. Detailed memory mapping and platform behavior belong to their respective specifications.

DIV and REM use signed operands; DIVU and REMU use unsigned operands. In MR8Sim, division by zero returns 0xFFFFFFFF for division and the dividend for remainder. Signed division of INT32_MIN by -1 returns INT32_MIN, and the corresponding remainder is zero.

MSB and MSBI search a 32-bit value for a selected bit value. Their signed control selects direction and starting position; controls with magnitude 64 or greater trap. If no matching bit is found, the result is 32.

System Bus access

SB and SBI are privileged operations. Their control value selects a System Bus word and whether to read or write; a read places the value in rd, while a write uses the source register selected by rs1. The simulator’s System Bus interface has 32 word addresses, numbered 0 through 31. System Bus use from user-mode code is rejected by the processor’s privilege check.

See the separate System Bus and SB/SBI specification for the detailed contract.

Traps

MTR does not occupy an opcode in this ISA. Traps and faults are handled by processor mechanisms and are not encoded as executable MTR instructions.

Versioning

This specification describes the ISA behavior implemented at baseline 61039f1. The document version identifies this article revision; it is distinct from a hardware or software release version. Changes to encoding or observable instruction behavior must be reviewed against MR8Sim and the RTL.