Memora8

As of October 4, 2026, the Memora8 FPGA implementation combines eight 32-bit CPU cores, 1 MiB of banked SRAM, MMU page windows, SYSTEM BUS devices, PageMover, DDR3/MIG connectivity, and UDP debug for the BX72 Artix-7 XC7A200T. The completed routed build meets 125 MHz timing, but the reported integration tests use a simulated DDR3/MIG and bypass physical Ethernet MAC/RGMII; board-level operation and the planned cryptographic accelerators remain future work.

Memora8 is developing a formal verification path for real SystemVerilog modules. This article explains why simulation and formal methods complement each other, how RTL properties are checked, what the current SystemVerilog subset supports, how SJP binds results to RTL and contracts, and why verification claims are made property by property.

A report on finalizing the baseline Memora8 cluster memory geometry: 8 CPUs, 16 physical shared banks, 32 logical banks, 128 pages of 8 KiB, and 1 MiB SRAM. The K4,4 topology routed on an Artix-7 XC7A200T at 125 MHz with positive timing slack and one-cycle CPU reads; full integration with the MMU and other processor blocks remains to be verified.

Memora8 has moved from the mr8sim simulator to a working networked MR8 processor on an Artix-7 XC7A200T FPGA. This report explains the hardware profile, transport protocols, memory ownership model, timing work, verification results, and next steps.

Memora8 gained adaptive SmallFIFO width and programmable CPU sleep, reducing overhead, improving BLAKE3 throughput, and keeping digest output unchanged.

Memora8 BLAKE3 benchmark report: eight simple processors, sustained aggregate IPC above 4.6, constant SRAM usage, and a predictable in-order pipeline.

A short overview of Memora8: 32-bit ISA, predictable pipeline, explicit memory model, and system/user separation for analysis and compiler work.

Memora8 Application Binary Interface Document version: 1.0 Status: Specification Compiler implementation baseline: SekuraJS 6dd5716 This document describes the function-call and data-layout conventions used by the SekuraJS Memora8 backend. It defines how compatible functions exchange scalar arguments and results, preserve registers, and use the stack. It supplements the Memora8 ISA specification; it does not change instruction behavior. Data model Property Convention General-purpose register width 32 bits ABI word size 4 bytes Pointer size 4 bytes Stack alignment at function boundaries 4 bytes Stack direction Grows toward lower addresses The compiler’s integer scalar types are i8, u8, i16, u16, i32, and u32. Their storage sizes and natural alignments are 1, 2, or 4 bytes. Pointers occupy 4 bytes. Structure fields are placed at their natural alignment, and the complete structure size is rounded up to the greatest field alignment. Arrays contain consecutive elements. ...

Memora8 Instruction Set Architecture Document version: 0.1 Status: Published specification Implementation baseline: Memora8 commit 61039f1 Overview Memora8 is a 32-bit processor architecture with 32 general-purpose registers and fixed-width, 32-bit instruction words. Its 5-bit opcode field defines 32 opcode values. The instruction set includes integer arithmetic and logic, shifts, comparisons, branches and jumps, 32-bit loads and stores, multiplication, division and remainder, bit search, and privileged System Bus access. MTR is not a program instruction or opcode; trap handling is a processor mechanism. ...

Memora8 System Bus and SB/SBI Instructions Document version: 1.0 Status: Specification Purpose The System Bus is Memora8’s privileged control interface for processor and device operations. It is separate from ordinary program memory: LW and SW access addresses through the CPU’s memory and MMU path, while SB and SBI access the System Bus contract directly. The System Bus is intended for control and status exchange, device commands, and platform services rather than general-purpose data storage. ...