Memora8: Memory Architecture Finalized, 125 MHz Timing Closed on Artix-7

AI Summary: Memora8 has defined a baseline cluster memory organization with 8 CPUs, 16 physical shared banks, 32 logical banks, 128 pages of 8 KiB, and 1 MiB of SRAM. Experiment mr8_mem_067 validates a complete bipartite K4,4 connection topology on an AMD/Xilinx Artix-7 XC7A200T-FBG484-2 at 125 MHz. The routed design reports WNS +0.025 ns, zero total negative setup or hold slack, 256 RAMB36 blocks used, and one-cycle IFD and MEM reads. The results show that physical connectivity and routing, rather than SRAM capacity alone, determine whether the cluster meets timing. Integrating the MMU, structured page_ref, PageMover, and Function Devices remains future work, and the 125 MHz result must be revalidated after that integration.

Memora8 has reached one of its key architectural milestones: the memory organization of a compute cluster has been defined, and experiments have confirmed that it meets timing on the target FPGA.

The baseline configuration of one cluster is:

• 8 CPUs
• 32 logical memory banks
• 4 pages per logical bank
• 128 pages
• 8 KiB per page
• 1 MiB of SRAM per cluster

Physically, this memory is implemented as 16 shared banks × 8 pages.

Each physical bank connects two CPUs and is logically divided into two four-page halves. The same 128 physical pages are therefore represented architecturally as 32 logical banks × 4 pages.

The latest experiment, mr8_mem_067, confirmed this physical organization on an AMD/Xilinx Artix-7 XC7A200T-FBG484-2 running at 125 MHz.

Why Memory Became the Key Question

For Memora8, defining the amount of SRAM was not enough. The main question was connectivity.

Giving every one of eight CPUs direct access to every memory bank looks simple at the logical level, but on an FPGA it quickly creates a different problem: long routing paths between CPUs and Block RAM.

This became clear throughout the experimental series.

With four CPUs and ten banks, full connectivity was still practical. Experiment mr8_mem_062 closed at 125 MHz while preserving direct one-cycle memory reads:

• WNS: +0.045 ns
• TNS: 0
• WHS: +0.121 ns
• failing setup/hold endpoints: 0

But scaling the same approach to eight CPUs caused the global interconnect to fail timing.

Experiment mr8_mem_061 used eight CPUs and 16 banks with global memory connectivity and produced:

• WNS: −1.418 ns
• TNS: −1250.470 ns
• 2,690 setup failing endpoints

The limiting factor was not the computation logic itself, but the physical routing across the FPGA.

This determined the next direction: instead of a global crossbar, memory needed a topology based on local connections.

The Cube Experiment

The next design organized eight CPUs as the vertices of a cube.

Experiment mr8_mem_064 used:

• 8 CPUs
• 24 shared banks on cube edges
• 8 private banks
• 32 banks in total
• 4 pages per bank
• 128 pages
• 1 MiB of SRAM

Each CPU directly saw only seven nearby banks rather than the entire cluster memory:

• 6 shared banks
• 1 private bank

This gave each CPU 224 KiB of directly reachable SRAM. Direct IFD and MEM reads still remained one-cycle operations.

The routed result at 125 MHz was:

• 18,893 LUTs
• 9,302 FFs
• 256 RAMB36
• WNS: +0.001 ns
• TNS: 0
• WHS: +0.090 ns
• routing errors: 0

Vivado reported that all user-specified timing constraints were met.

This was an important result: eight CPUs, 1 MiB of SRAM, and one-cycle reads could coexist if global connectivity was removed. However, the setup timing margin was only one picosecond, so the search for a better topology continued.

Final Physical Topology: K4,4

The latest experiment, mr8_mem_067, uses a different structure.

The eight CPUs are divided into two groups:

A = {0, 2, 4, 6}
B = {1, 3, 5, 7}

Every CPU in one group is connected to every CPU in the other group. The result is a complete bipartite graph, K4,4, with 16 physical shared banks between the processors.

Each bank contains:

8 pages × 8 KiB
= 64 KiB

In total:

16 banks × 8 pages
= 128 pages

128 × 8 KiB
= 1 MiB SRAM

Unlike the cube design, there is no separate class of private banks. All physical banks have the same structure.

32 Logical Banks

Although the memory is physically implemented as 16 banks with eight pages each, the architectural model represents it as:

32 logical banks
× 4 pages
× 8 KiB
= 1 MiB

Each physical shared bank connects two CPUs. Its eight pages are logically divided between its two endpoints:

CPU A -> 4 pages
CPU B -> 4 pages

Each CPU therefore receives four logical banks. With symmetric allocation:

4 banks × 4 pages
= 16 pages per CPU

16 × 8 KiB
= 128 KiB

Together, the eight CPUs use all 128 pages in the cluster.

The logical CPU / bank / page organization also makes it possible to assign pages a compact structured identity without exposing the physical placement of BRAM resources inside the FPGA to the software architecture.

Physical Bank Structure

In mr8_mem_067, each physical bank contains eight independent single-port RAMs:

8 × 2048 × 32 bit

Vivado implements every page as an individual single-port memory.

For each of its two CPU endpoints, the bank provides separate paths:

IFD    — direct instruction read
MEM    — normal CPU read/write
FD_R   — Function Device read
FD_W   — Function Device write

A physical bank therefore contains eight logical bank-side channels.

Each physical page remains single-port, so two operations can execute simultaneously only when they target different pages.

CPU Reads Remain One-Cycle

One of the main goals of the experimental series was not simply to fit 1 MiB of SRAM into the design, but to preserve a fast CPU-to-memory path.

In mr8_mem_067:

• IFD read = 1 cycle
• MEM read = 1 cycle

The Memora8 latency convention is:

request asserted before T1
BRAM accepts the address at T1
data is visible during T1..T2
CPU captures the result at T2

=> latency = 1 cycle

MEM writes remain pipelined through two stages, W0 + W1. This is intentional: the read path remains as short as possible, while the more complex write routing is absorbed by the pipeline.

Final FPGA Experiment

mr8_mem_067 was synthesized and fully routed using:

Vivado 2025.2
Device: xc7a200t-fbg484-2
Clock: 125 MHz
Period: 8.000 ns

Final routed timing:

WNS   +0.025 ns
TNS    0.000 ns

WHS   +0.075 ns
THS    0.000 ns

WPWS  +3.500 ns

All specified timing constraints were met.

Resource utilization:

LUT       23,205
FF         7,999
RAMB36       256
RAMB18         0
DSP            0

Of the 365 available RAMB36 blocks, 256 are used: 70.14% Block RAM utilization.

The design was fully routed:

logical nets           42,007
routable nets          33,275
fully routed nets      33,275
routing errors              0

What Limits the Clock Frequency

The experiment also shows where the real limit of this architecture lies.

The worst setup path was:

Requirement       8.000 ns
Data Path Delay   7.103 ns

Logic             1.327 ns
Route             5.776 ns

That means:

• logic: 18.7%
• routing: 81.3%

Once again, the primary limitation is not logic depth but physical routing distance across the FPGA.

Notably, the worst path crossed one of the longer connections introduced by the K4,4 topology, between CPU 3 and CPU 6. Even that path still met 125 MHz timing.

The remaining margin is small: +0.025 ns. Adding extra decode logic, an MMU, or other components directly into the fast read path must therefore be validated with separate post-route experiments.

Why We Did Not Stop at the First Working Design

Several different approaches were tested before arriving at the current topology:

• a universal crossbar;
• 32 banks × 4 pages;
• different read/write pipeline depths;
• fully shared memory;
• private and shared memory;
• cube topology;
• K4,4.

Some variants were logically correct but failed physical timing.

For example, a fully shared design with high global connectivity could not meet 125 MHz. A hybrid architecture using private pages and a shared pool, on the other hand, met 125 MHz even with 64 shared pages:

This confirmed the broader conclusion: SRAM capacity itself is not the main problem. The critical factor is the structure of the connections between CPUs and memory.

The final architecture was selected because it survived physical implementation.

What Can Now Be Considered Defined

After this series of experiments, the baseline Memora8 cluster memory has a clear structure:

1 cluster

8 CPUs

16 physical shared banks
× 8 pages
= 128 physical pages

logically:

32 banks
× 4 pages

page size = 8 KiB

total SRAM = 1 MiB

clock = 125 MHz

IFD read = 1 cycle
MEM read = 1 cycle

The physical K4,4 topology has already been confirmed by post-route results on the Artix-7 XC7A200T.

The next stage is no longer about searching for a new basic memory geometry. It is about integrating this structure with the rest of Memora8: the MMU, structured page_ref, PageMover, and Function Devices.

One important verification remains: preserving 125 MHz operation and one-cycle reads after the complete processor logic is integrated.

But the central question of this development stage has now been answered:

Eight CPUs and 1 MiB of paged SRAM can be physically connected inside a single Memora8 cluster while operating at 125 MHz and preserving direct one-cycle CPU reads.