Memora8 MACC8: INT8 Computation, Memory Bandwidth, and FPGA Timing — A One-Week Optimization Study
The final Memora8 MACC8 configuration uses 16 parallel signed INT8 multiplications, a 128-bit datapath, four dedicated 8 KiB SRAM pages, and a 128-bit PM1 DDR3 transfer interface. Eight partial-result modes and a 128-entry FIFO provide asynchronous execution and result collection. The complete Artix-7 XC7A200T design closes timing at 125 MHz with +0.050 ns setup slack. On-board measurements reached 0.352 GMAC/s for freshly loaded 16 KiB operand pairs and 0.628 GMAC/s when reusing one operand page, including the DDR3 transfer and CPU control cycle.