Memora8 is developing a formal verification path for real SystemVerilog modules. This article explains why simulation and formal methods complement each other, how RTL properties are checked, what the current SystemVerilog subset supports, how SJP binds results to RTL and contracts, and why verification claims are made property by property.
A report on finalizing the baseline Memora8 cluster memory geometry: 8 CPUs, 16 physical shared banks, 32 logical banks, 128 pages of 8 KiB, and 1 MiB SRAM. The K4,4 topology routed on an Artix-7 XC7A200T at 125 MHz with positive timing slack and one-cycle CPU reads; full integration with the MMU and other processor blocks remains to be verified.
Sekura JS now verifies the compiled SOBJ artifact against formal SJV contracts. This article explains the source-to-proof pipeline, preconditions, postconditions, symbolic execution, SAT and UNSAT results, counterexample diagnostics, verification identity, and the limits of the current system.
Memora8 has moved from the mr8sim simulator to a working networked MR8 processor on an Artix-7 XC7A200T FPGA. This report explains the hardware profile, transport protocols, memory ownership model, timing work, verification results, and next steps.
A first post in the Sekura Talk cycle: why we built a live conversation layer without permanent history, how it works, and what public testing is meant to validate.
A category-style article about why the internet needs a simpler conversation layer: public talk, less profile friction, less algorithmic mediation, and more user control.
AI needs more than documents and tools. It needs an Expert AI Layer: structured human judgment, methods, rules, and exceptions that help models act like experienced professionals.
A simplified English overview of the Reganta boot path from ROM to a running system, including RAW images, verified modules, PageMover transfer, and atomic CPU_RESTART.
Memora8 gained adaptive SmallFIFO width and programmable CPU sleep, reducing overhead, improving BLAKE3 throughput, and keeping digest output unchanged.
Reganta is an OS theory centered on streams, modules, and page-based memory coordination across Function Devices, with a contract model suited to AI-driven systems.