From October 3 to 10, 2026, Memora8 added physical microSD, UART, and GPIO tests, integrated BLAKE3 and Ed25519 VERIFY, and optimized PageMover while retaining a routed 125 MHz eight-core Artix-7 build. This report summarizes the measured results and the next steps: a custom Ethernet controller and incremental formal verification.
As of October 4, 2026, the Memora8 FPGA implementation combines eight 32-bit CPU cores, 1 MiB of banked SRAM, MMU page windows, SYSTEM BUS devices, PageMover, DDR3/MIG connectivity, and UDP debug for the BX72 Artix-7 XC7A200T. The completed routed build meets 125 MHz timing, but the reported integration tests use a simulated DDR3/MIG and bypass physical Ethernet MAC/RGMII; board-level operation and the planned cryptographic accelerators remain future work.
Memora8 is developing a formal verification path for real SystemVerilog modules. This article explains why simulation and formal methods complement each other, how RTL properties are checked, what the current SystemVerilog subset supports, how SJP binds results to RTL and contracts, and why verification claims are made property by property.
A report on finalizing the baseline Memora8 cluster memory geometry: 8 CPUs, 16 physical shared banks, 32 logical banks, 128 pages of 8 KiB, and 1 MiB SRAM. The K4,4 topology routed on an Artix-7 XC7A200T at 125 MHz with positive timing slack and one-cycle CPU reads; full integration with the MMU and other processor blocks remains to be verified.
Memora8 has moved from the mr8sim simulator to a working networked MR8 processor on an Artix-7 XC7A200T FPGA. This report explains the hardware profile, transport protocols, memory ownership model, timing work, verification results, and next steps.